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AR# 33885

LogiCORE IP Display Port v1.1 - Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?

Description

Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?

Solution

This is because there is an extra "." in the <core name>.vho port list that needs to be removed. 

 

You can fix this by removing the "." from in front of all the ports. 

There is a sample of some of the ports. 

From: 

 

your_instance_name : core 

port map ( 

.reset => reset, 

.apb_clk => apb_clk, 

.apb_select => apb_select, 

.apb_enable => apb_enable, 

.apb_write => apb_write, 

.apb_addr => apb_addr, 

.apb_wdata => apb_wdata, 

.apb_int => apb_int, 

.apb_rdata => apb_rdata, 

... 

 

 

 

To: 

 

your_instance_name : core 

port map ( 

reset => reset, 

apb_clk => apb_clk, 

apb_select => apb_select, 

apb_enable => apb_enable, 

apb_write => apb_write, 

apb_addr => apb_addr, 

apb_wdata => apb_wdata, 

apb_int => apb_int, 

apb_rdata => apb_rdata, 

... 

 

 

 

 

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE Display Port Release Notes and Known Issues.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 33885
Date Created 11/30/2009
Last Updated 05/23/2014
Status Archive
Type General Article