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AR# 33888

LogiCORE IP Display Port v1.2 - The example design does not meet timing when I target a Spartan-6 device. Why?

Description

Why does the example design fail to meet timing when I target a Spartan-6 device?

Solution

The timing for the Spartan-6 device is very tight and requires the use of area constraints in order to meet timing. 

There are some constraints in the example design UCF to help meet timing, however in some cases the user will need to modify the area constraints to meet timing. 

You can modify the constraints using the PlanAhead tool, or by editing the UCF file in a text editor. 

You can also change the map options (-register_duplication, -logic_opt, -retiming), or apply an area group.

For a detailed list of LogiCORE IP Display Port Release Notes and Known Issues, see (Xilinx Answer 33258).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35180 Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA N/A N/A
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 33888
Date Created 11/30/2009
Last Updated 08/05/2014
Status Active
Type General Article
IP
  • DisplayPort