The timing for the Spartan-6 device is very tight and requires the use of area constraints in order to meet timing.
There are some constraints in the example design UCF to help meet timing, but in some cases, the user might need to modify the area constraints to meet timing.
You can modify the constraints using the PlanAhead tool, or by editing the UCF file in a text editor.
Youmight also want to tryto changethe map options (-register_duplication, -logic_opt, -retiming), or to apply an area group.
For a detailed list of LogiCORE IP Display Port Release Notes and Known Issues, see (Xilinx Answer 33258).
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33258 | LogiCORE IP DisplayPort - Release Notes and Known Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 35180 | Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA | N/A | N/A |
| 33258 | LogiCORE IP DisplayPort - Release Notes and Known Issues | N/A | N/A |