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LogiCORE IP Display Port v1.1 - Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2 bits wide?

AR# 33890

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Topic IP-DSP MVI
Last Updated 12/01/2009
Status Active
Description

Keywords: display port, dual, 2-wide, FORCE_DUAL_PIXEL, USER_PIXEL_WIDTH, DPCD_LANE_COUNT_SET

Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2-bits wide?

This happens when the following registers are set:
(Sink only)
0x008 FORCE_DUAL_PIXEL = 0x01
0x010 USER_PIXEL_WIDTH = 0x02
0x404 DPCD_LANE_COUNT_SET = 0x01

Solution

To work around this issue, you should not force the user interface to be 2 bits wide.
Work around is to set FORCE_DUAL_PIXEL = 0x00

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE Display Port Release Notes and Known Issues.

 
 
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