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AR# 33902

Virtex-4/-5 - What is the CLKA -> CLKB clock-to-clock setup time of the block RAM (Tbccs)?


A value for Tbccs is specified in the data sheets for the Virtex-II and Virtex-II Pro devices. What are the values for the Virtex-4/-5 devices? How do I calculate the value of Tbccs?


For an explanation of the "Tbccs" parameter, please see (Xilinx Answer 5894).

Tbccs is the same as the total block RAM minimum clock period (min pulse high + min pulse low) = (Tbpwh + Tbpwl).

For the Virtex-4 the maximum RAM frequency is 500 MHz (-12 grade), so the Tbccs = 2 ns.

For the Virtex-5 the maximum RAM frequency is 550MHz (-3 grade), so the Tbccs = 1.818 ns.

AR# 33902
Date Created 12/02/2009
Last Updated 12/15/2012
Status Active
Type General Article