11.3 System Generator for DSP - Why do I sometimes see cycle mismatches between my Simulink and HDL simulations when I use a really small sample period?
Description
Keywords: rate, sysgen, period
When I use a small sample period on the order of my actual clock, I sometimes see different latencies and results than expected.
Solution
This is because of a known issue with the way System Generator interacts with the Simulink solver.To work around this issue, it is recommended that you use normalized integer rates, such as normalizing all your clocks to a period of 1.
This issue has been resolved in System Generator 11.4.