UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33909

11.3 System Generator for DSP - Why do I sometimes see cycle mismatches between my Simulink and HDL simulations when I use a really small sample period?

Description

When I use a small sample period on the order of my actual clock, I sometimes see different latencies and results than expected.

Solution

This is because of a known issue with the way System Generator interacts with the Simulink solver.  

 

To work around this issue, it is recommended that you use normalized integer rates, such as normalizing all your clocks to a period of 1. 

 

This issue has been resolved in System Generator 11.4.

AR# 33909
Date Created 12/02/2009
Last Updated 05/23/2014
Status Archive
Type General Article