We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33914

Virtex-6 FPGA MMCM - What are the addresses and values for dynamic reconfiguration of the MMCM through the DRP?


The DRP functionality for the Virtex-6 FPGA MMCM is supported through an Application Note and associated reference design.


Xilinx XAPP878 MMCM Dynamic Reconfiguration describes the DRP feature in detail. An HDLreference design is provided along with the Application Note. The reference design uses a state machine to drive the DRP and ensures the registersare controlled in the correct sequence.
AR# 33914
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Page Bookmarked