The root is not able to accept reads and writes because of some parameter settings in the top level root port file and because the command register of the root port is not set to accept memory or I/O transactions.
Follow the instructions below to allow memory and I/O transactions to pass to the user interface of the root port testbench. The files referenced in steps 2 and 3 below can be found at this location.
http://www.xilinx.com/txpatches/pub/applications/pci/ar33918.zip 1. Make the following changes to the parameters in the pcie_2_0_rport_v6.v file found in the <core name>/simulation/dsport directory.
parameter BAR0 = 32'h00000000,
parameter BAR1 = 32'h00000000,
parameter BAR2 = 32'h00FFFFFF,
parameter BAR3 = 32'hFFFF0000,
parameter BAR4 = 32'hFFF0FFF0,
parameter BAR5 = 32'hFFF1FFF1,
parameter DISABLE_BAR_FILTERING = "TRUE",
parameter DISABLE_ID_CHECK = "TRUE",
parameter DISABLE_RX_TC_FILTER = "TRUE",
parameter HEADER_TYPE = 8'h01,
parameter PCIe_CAP_DEVICE_PORT_TYPE = 4'b0100,
2. Replace the pci_exp_usrapp_cfg.v with the one that is included in the zip file. This file provides the tasks necessary to make the write to the command register using the back end configuration port.
3. Call the task TSK_WRITE_CFG_DW in your testbench as shown below before you issue your first write from the endpoint:
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);
See the sample_smoke_test1.v file in the zip file as an example
Revision History 12/09/2009 - Initial Release