We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33918

Virtex-6, Spartan-6 FPGA and Block Plus Integrated Block Wrappers for PCI Express- Why is the root port model and testbench provided with the example simulation not passing Memory or I/O transactions to the user side interface?


Known Issue: Virtex-6 FPGA: v1.4, v1.3, v1.2, v1.1; Spartan-6 FPGA: v1.2, v1.1; Block Plus v1.13, v1.12

The root port model provided with the example simulation is not passing memory or I/O transactions to the user side interface. Is there a way to allow the root port testbench to accept these transactions?


The root is not able to accept reads and writes because of some parameter settings in the top level root port file and because the command register of the root port is not set to accept memory or I/O transactions.

Follow the instructions below to allow memory and I/O transactions to pass to the user interface of the root port testbench. The files referenced in steps 2 and 3 below can be found at this location.


1. Make the following changes to the parameters in the pcie_2_0_rport_v6.v file found in the <core name>/simulation/dsport directory.

parameter BAR0 = 32'h00000000,

parameter BAR1 = 32'h00000000,

parameter BAR2 = 32'h00FFFFFF,

parameter BAR3 = 32'hFFFF0000,

parameter BAR4 = 32'hFFF0FFF0,

parameter BAR5 = 32'hFFF1FFF1,


parameter DISABLE_ID_CHECK = "TRUE",


parameter HEADER_TYPE = 8'h01,

parameter PCIe_CAP_DEVICE_PORT_TYPE = 4'b0100,

2. Replace the pci_exp_usrapp_cfg.v with the one that is included in the zip file. This file provides the tasks necessary to make the write to the command register using the back end configuration port.

3. Call the task TSK_WRITE_CFG_DW in your testbench as shown below before you issue your first write from the endpoint:

board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);

See the sample_smoke_test1.v file in the zip file as an example

Revision History

12/09/2009 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 33918
Date Created 12/09/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 Integrated Endpoint Block
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )