11.x ChipScope Pro tool - IBERT - Virtex-6 FPGA - Clock Pattern on Reflck is incorrect
Description
Keywords: GTX, GTP, GTH, transceiver, BER, probe, clk, clock, frequency, BERT, XBERT, LogiCORE, IBERT
When I probe the Refclk on my Virtex-6 FPGA IBERT design, I do not see the clock frequency I expect. What is the issue here?
Solution
This issue will occur when you use the 16-bit data width. To work around it, regenerate for 20-bit data width. If you require further assistance with this, please open an online WebCase with Xilinx Customer Support:http://www.xilinx.com/support/clearexpress/websupport.htm