If I simulate a design that utilizes the external Clock Correction Module generated by the Virtex-5 FPGA RocketIO Wizard, the following warning appears:
"Warning: At time 55134250, RDEN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl
k1 is high when RST is high. RDEN should be low during reset."
This warning can safely be ignored without impacting the functionality of the simulation. This is not a concern for hardware implementations.