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AR# 33929

Serial RapidIO v5.4 - Incorrect reference clock in VHDL example sim (3.125, 156.25 MHz refclk)


The ep_tb.vhd is incorrect for line rate of 3.125G with 156.25 MHz reference clock. It gives 312.5 MHz as the reference clock instead of 156.25 MHz. This only applies to the VHDL example for Virtex-5, Virtex-6 and Spartan-6 FPGA.


To fix the issue, change the following statement in the sys_clk_gen_inst and sys_clk_gen_sim instances:


halfcycle => 1600 ps -- 312.5 MHz system clock to the core


halfcycle => 3200 ps -- 156.25 MHz system clock to the core

This issue will be fixed in v5.5 of the core.

AR# 33929
Date Created 12/07/2009
Last Updated 12/15/2012
Status Active
Type General Article