Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Missing UCF constraint for x1, x2, and x4 Gen1 designs with a User Interface Clock of 250 MHz
Description
Known Issue: v1.4
The UCF file for x1, x2, and x4 Gen1 designs using a 250 MHz User Interface (trn_clk) frequency is missing a timing constraint.
Solution
To fix this, open the generated UCF file found in the <core name>/example_design directory and add the following based on if you are doing an endpoint design or root port design and the reference clock selected. In each case, change the priority on the existing constraint in the UCF named TIMSPEC "TS_CLK_125" from a 1 to a 10.
Endpoint with 100 MHz Reference Clock
NET "core/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;
Endpoint with 125 MHz Reference Clock
NET "core/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2 HIGH 50 % PRIORITY 1;
Endpoint with 250 MHz Reference Clock
NET "core/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*1 HIGH 50 % PRIORITY 1;
Root Port with 100 MHz Reference Clock
NET "cgator_wraper/rport/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;
Root Port with 125 MHz Reference Clock
NET "cgator_wraper/rport/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2 HIGH 50 % PRIORITY 1;
Root Port with 250 MHz Reference Clock
NET "cgator_wraper/rport/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*1 HIGH 50 % PRIORITY 1;
Revision History
12/11/2009 - Initial Release
Applies To
IP
- Virtex-6 FPGA Integrated Endpoint Block for PCI Express