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AR# 33957

MIG v3.3, DDR3 Virtex-6 FPGA - ZQ Short Calibration Commands are not seen in simulation or hardware


The MIG Virtex-6 FPGA DDR3 design includes ZQ Short (ZQCS) and ZQ Long (ZQCL) Calibration commands that adhere to the DDR3 JEDEC Standard. If I run the MIG v3.3 design through simulation or in hardware, the ZQCL command is observed during initialization, but not during normal operation.


This is a problem with a parameter setting in the MIG v3.3 Virtex-6 FPGA DDR3 design.

To work around this issue:

  1. open the "memc_ui_top.v" module.

    This is located in both the example_design/rtl/ip_top and user_design/rtl/ip_top directories.
  2. Locate the parameter declaration for tZQI. It is set as follows:

    parameter tZQI = 128,

    This setting is not accurate, preventing ZQCS commands from being sent.
  3. Change the setting to 256 as follows:
    parameter tZQI = 256,

    This parameter is set correctly in MIG 3.4, which is released with ISE Design Suite 12.1.
AR# 33957
Date Created 12/14/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG