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AR# 3396

M1.4 PAR - XC4000 design crashes after starting the Initial Timing Analysis.


See similar but different issue covered by Solution 3317.

There is a known map bug that will lead to a crash in PAR
during initial timing analysis. The problem is caused by
clock configurations where an internal signal drives a buffer
that in turn drives a clock buffer. Map correctly optimizes
the buffer out of the design but loses the connection to the
clock buffer. The driver-less clock buffer leads to a crash
in PAR.



This problem can be avoided by placing a NOMERGE property
on the signal driving the clock buffer and re-mapping the
design. The following .ucf constraint will accomplish this:

NET "net_name" KEEP ;

The map bug is scheduled to be fixed in the upcoming M1.5


This problem is fixed in the latest M1.4 Core Tools Patch available on the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip

AR# 3396
Date Created 02/06/1998
Last Updated 04/03/2000
Status Archive
Type General Article