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AR# 33994

Virtex-6 FPGA GTX Transceiver Wizard: Selecting "No TX" limits use of REFCLK0_Q0 for RX PLL

Description

When the "No TX" check box is used and the RX line rate and clocking parameters are changed from the default, selecting REFCLK0_Q0 results in an error when the core is generated.

The error message will read as follows:

"Validation Failed

TX/RX line rates differ, must use different clock sources
TX/RX line rates differ, must use different clock sources"

Solution

This error is a result of the TX clocking settings still being set and checked against when "No TX" is selected. 

To work around this issue, select a line rate and reference clock rate that match the desired RX settings before checking the "No TX" box.

Once this is done, the Wizard will see that the reference clock is correct for both the RX and TX, and allow for the use of REFCLK0_Q0. 

This is a known issue for versions 1.4 and earlier and will be corrected in future versions of the core.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 33994
Date 06/23/2017
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
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