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AR# 33995

MIG 3.3, Virtex-6 FPGA DDR3 - Write Leveling does not succeed and calibration fails due to IDELAYCTRL not being automatically inferred by the software

Description

When I run a multi-component or DIMM Virtex-6 FPGA DDR3 MIG design in hardware, Write Leveling does not complete which causes calibration to fail. This specific Write Leveling failure can be detected by:
  • DQS not toggling on the FPGA output
  • No DQ transition detected
  • The signal dlyval_dqs_early found in the "phy_dly_ctrl.v" module is always 0

Calibration failure is detected by:

No assertion on phy_init_done

Solution

If Write Leveling does not complete, it is important to check that the IDELAYCTRL blocks are being placed properly.There is a problem currently being investigated in the implementation tools that causes IDELAYCTRL blocks to not be replicated properly.

In the MIG design, a singleIDELAYCTRL is instantiated in "iodelay_ctrl.v" with the IODELAY_GROUP parameter enabled.With this configuration, the implementation tools should replicate this block for each bank where an IODELAY is used.

In the MIG design, IODELAY components are usedin the capture clock and resynchronization clocklogic.Thus, any bank where either capture or rsync logic is placed requires an IDELAYCTRL.The capture clock logic is always placed in the same bank(s) as the data groups, but the rsync logic might be placed in Address/Control and System Clock banks (in addition to data banks). For full details on rsync (BUFR) allocation rules, see the Virtex-6 Memory Interface Solutions User Guide (UG406). When the rsync logic is placed in a non-data bank (i.e., Addr/Cont or Sys Clock), the implementation tools are not properly allocating IDELAYCTRLs in these banks.

To work around this issue, manually instantiate and LOC the IDELAYCTRL for all banks where IODELAYs are used.

1. Modify iodelay_ctrl.v as follows for the IDELAYCTRL instantiation:

//Begin Edit

(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl_0
(
.RDY (iodelay_ctrl_rdy_0),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);

IDELAYCTRL u_idelayctrl_1
(
.RDY (iodelay_ctrl_rdy_1),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);


assign iodelay_ctrl_rdy = iodelay_ctrl_rdy_0 && iodelay_ctrl_rdy_1;

//End Edit
NOTE: This example is for a MIG design requiring two IDELAYCTRLs, additional IDELAYCTRLs might need to be manually instantiated based on the number of banks that use IODELAY components.

2. Add LOC constraints to the UCF for each IDELAYCTRL instance # as follows:
INST "u_iodelay_ctrl/u_idelayctrl_#" LOC = IDELAYCTRL_X_Y_;

NOTE: To determine the XY coordinates, use FPGA editor to locate the IDELAYCTRL in each bank that it is needed.When you click on the block, it shows the coordinates(IDELAYCTRL_X_Y_) in the console window.

This issue has been fixed starting in ISE 12.1 software using MIG v3.4.

AR# 33995
Date Created 12/20/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
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IP
  • MIG