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AR# 34014

Serial RapidIO v5.4 - Problems with VIO Example Design


The ChipScope tool VIO Example Design that is generated with v5.4 of the Serial RapidIO Endpoint Solution has several problems, including the following:
  • The Verilog design sends one too many transactions of each type for each sequence
  • The VHDL design can lock up, often after the first transaction
  • The ChipScope project file only works for boards where the device is second in the JTAG chain
  • Randomize size is on by default


The followingare updated ZIP files that resolve the issues for both Verilog or VHDL-generated example designs using 8-bit Device IDs. Follow the instructions in the README files to install the update. If you are using a 16-bit Device ID and require the updated files, please contact Xilinx Technical Support and reference this Answer Record.

Verilog: 34014_ver.zip

VHDL: 34014_vhdl.zip

These updated files are to be included in the v5.5 release of the Serial RapidIO Core.

AR# 34014
Date Created 12/22/2009
Last Updated 12/15/2012
Status Active
Type General Article
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