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AR# 34016

Virtex-5 GTP RocketIO Wizard: tx_sync module


The tx_sync module generated by the GTP RocketIO Wizard does not assert TXPMASETPHASE for the correct number of cycles when it is being used for only TX skew reduction. This answer record discusses what modifications can be made to the tx_sync module to align with the guidelines in UG196, the Virtex-5 FPGA GTP RocketIO User's Guide.


The tx_sync module uses the sync_counter_r register as a counter and pulls particular bits as enables for the next stage in the state machine. Modifications to this register need to be made to coincide with the GTP User's Guide for TX skew reduction:

1) Expand sync_counter_r to be [16:0]

2) Depending on the value of PLL_TXDIVSEL_COMM_OUT, sync_count_complete_r needs to be connected to one of three bits in the counter register:

1: sync_count_complete_r = sync_counter_r[14]

2: sync_count_complete_r = sync_counter_r[15]

4: sync_count_complete_r = sync_counter_r[16]

AR# 34016
Date 05/19/2012
Status Archive
Type Known Issues
  • Virtex-5 LXT
  • Virtex-5 SXT
  • ISE - 10.1
  • ISE Design Suite - 11.1
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  • ISE - 9.2i
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  • Virtex-5 RocketIO GTP Transceiver Wizard
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