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Virtex-6 Integrated Block Wrapper for PCI Express - Only Use v1.3 rev 2 (or later v1.3 revisions) for Virtex-6 FPGA Engineering Samples

AR# 34033

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Topic PCIe
Last Updated 11/14/2011
Status Active
Description

You might experience problems, such as link training issues, when using production core versions (v1.4 or later) of the Virtex-6 FPGA Integrated Block for PCI Express on Engineering Sample (ES) silicon.

Solution

Only version 1.3, rev 2 or later revisions of the v1.3 wrapper are supported on ES silicon. No other version is supported on ES silicon.

For more information on CES errata and how to know if your silicon is CES or not, see the Virtex-6 errata found in the Virtex-6 Documentation Center.

If you are targeting an ML605 board with ES silicon, use the v1.3, rev 2 core; see (Xilinx Answer 34009) for more information.

Revision History
11/14/2011- Updated statement about ML605
08/06/2010 - Updated text to clarify supported ES versions
12/22/2009 - Initial Release
Applies To

Devices

  • Virtex-6 LXT

IP

  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
 
 
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