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AR# 34033 Virtex-6 Integrated Block Wrapper for PCI Express - Only Use v1.3 rev 2 (or later v1.3 revisions) for Virtex-6 FPGA Engineering Samples

Description

You might experienceproblems, such as link training issues, when using production core versions (v1.4 or later)of the Virtex-6 FPGA Integrated Block for PCI Express on Engineering Sample (ES) silicon.

Solution

Only version 1.3, rev 2 or later revisions of the v1.3 wrapper are supported on ES silicon. No other version is supported on ES silicon.

For more information on CES errata and how to know if your silicon is CES or not,see the Virtex-6 errata found in the Virtex-6 Documentation Center.

Ifyou are targeting an ML605 board with ES silicon, use the v1.3, rev 2 core; see (Xilinx Answer 34009) for more information.

Revision History
11/14/2011- Updated statement about ML605
08/06/2010 - Updated text to clarify supported ES versions
12/22/2009 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
32929 Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA N/A N/A
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A
34432 Virtex-6 FPGA Connectivity Kit and Targeted Reference Design (TRD) - Release Notes and Known Issues N/A N/A
34009 Virtex-6 Integrated Block Wrapper for PCI Express- PCI Express link will not train on ML605 boards using ES silicon N/A N/A

Actions

AR# 34033
Date Created 12/22/2009
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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