When I run my Virtex-4 FPGA design on a Windows Vista machine with the Timing Driven Map option turned off, PAR appears to run to completion successfully, but then posts one of the following pop-up errors at the end of processing. Is this a known problem?
On a Windows XP machine, the error is as follows:
The messages printed in theISE console are as follows:
This problem only occurs withVirtex-4 FPGA designs using the non-timing driven flow (placement performed by PAR). Towork aroundthis issue,use the timing driven MAP flow (placement performed by MAP) which has the added value of improving QOR.
Due to limited exposure and an easy work-around, no fix is scheduled for this issue.