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AR# 34045

Config, BitGen, Spartan-6 - What are the minimum and maximum Master CCLK frequencies?


The Spartan-6 FPGA Data Sheet v1.1(DS162) switching characteristics list the minimum and maximum Master CCLK frequencies.

This information is also included in the BitGen options for CCLK, but the options for this setting exceed the specs in the data sheet.


The max BitGen CCLK setting that should be used is 26.

Settings 33, 50, and 66 exceed the max CCLK Freq specification and should not be used.

AR# 34045
Date Created 01/04/2010
Last Updated 01/22/2013
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4