AR# 34055 MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?

What are the requirements for the RZQ and ZIO pins?
How are the pins used in the design?

RZQ Usage

Phase 1 Calibration - The external resistor on the RZQ pin is measured during Phase 1 Calibration. This is performed using the Soft Calibration Module to determine the desired on-chip Input Termination value for several of the pre-defined MCB pins (e.g., DQ bus). This calibration stage is only performed when Calibrated Input Termination is enabled in the MIG tool. Enabling this feature requires the usage of VREF within the MCB bank because the Soft Calibration module relies on the VREF supply to perform the input termination calibration. See (Xilinx Answer 34046) for information regarding Calibrated Input Termination and VREF requirements for LPDDR.
Phase 3 Calibration - To compensate for voltage and temperature related shift of the DQS strobes, Phase 3 calibration runs continuously during normal operation. It uses the Soft Calibration Module to continuously monitor the tap delay values of the IDELAY elements used to delay the DQS input paths. If a shift in tap delay value is detected, the tap delay count on the DQS strobe input paths can be adjusted to keep them centered in the Read Data capture window. An IODRP2 primitive associated with the RZQ pin is used during Continuous DQS Tuning.

RZQ Requirements

The RZQ pin is required and cannot be removed from the design.
When using Calibrated Input Termination, the RZQ pin needs a resistor of value 2R from the pin to ground, where R is the desired input termination value.
When Calibrated Input Termination is not used, the RZQ pin can be left unconnected on the board.
The RZQ pin must be within the same I/O bank as the memory interface pins. Please note that data strobe pins are paired such that if only DQS is used(single-ended strobe) DQS_n is lost as a general I/O
The default location of the RZQ pin can be found in the MIG output UCF constraints files. This location can be moved to another free pin within the I/O bank unless using ES silicon. For ES silicon, please reference (Xilinx Answer 33130).
NOTE: Xilinx has not tested all possible RZQ locations, if the pin is moved it is important to ensure timing is met. Timing is guaranteed with the RZQ location provided by MIG.

ZIO Usage

The ZIO pin is used with the Calibrated Input Termination feature to calibrate the input termination value.
The ZIO pin is to be a "no connect" pin on the board. It is important that the pin be left completely floating, and not connected to ground or any voltage rail. The Calibrated Input Termination uses the ZIO pin in addition to the RZQ pin and the reference voltage on VREF to calibrate the internal Input Termination resistance, which is used when the FPGA is receiving DQ and DQS signals during a read cycle.
The ZIO pin is only required when using Calibrated Input Termination. If Calibrated Input Termination is not used, the ZIO pin can be removed from the MIG output UCF/design. By default, MIG 3.4 does not allocate the ZIO pin when Calibrated Input Termination is not selected.

ZIO Requirements

The ZIO pin needs to be connected toa bonded I/O site.
TheZIO pincannot have a board trace attached to this pin (no connect).
The ZIO pin must be placed within the same I/O bank as the memory interface pins. Please note that data strobe pins are paired such that if only DQS is used(single-ended strobe) DQS_n is lost as a general I/O
The default location of the ZIO pin can be found in the MIG output UCF constraints files. This location can be moved to another free pin within the I/O bank.
NOTE: Xilinx has not tested all possible ZIO locations, if the pin is moved it is important to ensure timing is met. Timing is guaranteed with the ZIO location provided by MIG.
The ZIO pin is only required when using Calibrated Input Termination. If this feature is not enabled, the ZIO pin can be removed from the MIG output UCF/Design.

Answer Number	Answer Title	Version Found	Version Resolved
34587	MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1	N/A	N/A

Answer Number	Answer Title	Version Found	Version Resolved
40780	MIG Spartan-6 MCB - FPGA Input Termination Options	N/A	N/A
34153	Spartan-6 FPGA MCB - Can MCB pins be swapped to help facilitate board layout?	N/A	N/A
34046	MIG v3.3-v3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported	N/A	N/A
34265	MIG Solution Center - MIG Virtex-6 and Spartan-6 Top Issues	N/A	N/A

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