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AR# 34066 SPI-4.2 v9.3 - MMCM VCO values outside of allowable range

Description

The SPI-4.2 core's clocking example designs use incorrect values for the MMCM attributes "DIVCLK_DIVIDE", "CLKFBOUT_MULT_F", and "CLKOUT0_DIVIDE_F" that may cause the MMCMs to operate outside of the supported range.

Solution

1) Sink Clock example design (pl4_snk_clk.v/vhd)

For the "mmcm0" instance of MMCM (connects to RDClk clock):

Change the value of "DIVCLK_DIVIDE" to 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.

All other parameters are correct.

2) Source Clock example design (pl4_src_clk.v/vhd)

For the "mmcmo" instance of MMCM ( connects to SysClk clock):

Change the value of "DIVCLK_DIVIDE" to 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.
All other parameters are correct.


For the "mmcm1" instance of MMCM ( connects to TSClk clock):

Change the value of "CLKFBOUT_MULT_F" to 9.0

Change the value of "CLKOUT0_DIVIDE_F" to 9.0

All other parameters are correct.

This issue is scheduled to be fixed in v10.1 of the core (available in ISE Design Suite 12.1).


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33313 SPI-4.2 v9.3, v9.3 Rev1 and v9.3 Rev2 - Release Notes and Known Issues for ISE 11.3/11.4/11.5 N/A N/A
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

Actions

AR# 34066
Date Created 01/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • SPI-4 Phase 2 Interface Solutions
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