This answer record identifies starting points when debugging hardware related issues to PCI Express.
NOTE: This answer record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.
The system is booting, but the endpoint is not recognized by hardware; see (Xilinx Answer 34777).
The system is hanging or locking up during the boot process or after data transfers begin; see (Xilinx Answer 35034).
the device is recognized, but problems occur during operation of the design; see (Xilinx Answer 35033).
For link training issues debugging guide (Virtex-5 Integrated PCI Express Block Plus); see (Xilinx Answer 42368).
Revision History
12/10/2011 - Added Answer Record42368
08/13/2010 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 39548 | Spartan-6 FPGA Integrated Block for PCI Express - Replay Timeout is occuring too fast when using VHDL wrapper | N/A | N/A |
| 35034 | Design Assistant for PCI Express - Completion Timeouts Cause the System to Freeze | N/A | N/A |
| 35033 | Design Assistant for PCI Express - Device is recognized by system, but problems occur | N/A | N/A |
| 34248 | Design Assistant for PCI Express - MSI interrupt is not received at the host | N/A | N/A |
| 39380 | Design Assistant for PCI Express - Receiver detect problems | N/A | N/A |
| 34777 | Design Assistant for PCI Express - Device not recognized by system | N/A | N/A |
| 34538 | Xilinx Solution Center for PCI Express - Design Assistant | N/A | N/A |
| 33251 | Design Assistant for PCI Express - Application Note xapp859 Design Does Not Return Completion for Memory Requests with Non-zero Attribute Field | N/A | N/A |