Solution

To determine if data errors are due to this address bus timing issue, delay can be inserted into each address bit path to move the window and avoid the possibility of a tIH violation. Xilinx has tested this delay insertion by instantiating ODELAY into each address bit output path and setting the delay to '0'. The added delay through the ODELAY component shifts the address bus timing to avoid a hold time violation.

To add ODELAY to each address bit, the "mcb_raw_wrapper.v" module (located in the MIG output 'rtl' directory) must be manually modified:

NOTE: If you are using the MPMC module in EDK, the file is located in $XILINX_EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_00_a\hdl\verilog where $XILINX_EDK is the location of the EDK install.

Step 1 - Add delay wire declarations

wire [C_MEM_ADDR_WIDTH-1:0]ioi_addr_delay;
wire [C_MEM_ADDR_WIDTH-1:0]t_addr_delay;

Step 2 - Modify the address output logic. Locate the generate statement for the address output (this starts at line 6300 in MIG 3.3).

Comment out the following code:

//// Address

genvar addr_i;
generate
for(addr_i = 0; addr_i < C_MEM_ADDR_WIDTH; addr_i = addr_i + 1) begin : gen_addr_obuft
OBUFT iob_addr_inst
(.I ( ioi_addr[addr_i]),
.T ( t_addr[addr_i]),
.O ( mcbx_dram_addr[addr_i])
);
end
endgenerate

Replace with:

//// Address

genvar addr_delay_i;
generate
for(addr_delay_i = 0; addr_delay_i < C_MEM_ADDR_WIDTH; addr_delay_i = addr_delay_i + 1) begin : gen_addr_delay_obuft
IODELAY2 #(
.ODELAY_VALUE (0), // 0 to 255 inclusive
.DELAY_SRC ("ODATAIN"),
.SIM_TAPDELAY_VALUE (50) // 10 to 90 inclusive
) delay_addr_inst
(.DOUT (ioi_addr_delay[addr_delay_i]),
.TOUT (t_addr_delay[addr_delay_i]),
.ODATAIN (ioi_addr[addr_delay_i]),
.T ( t_addr[addr_delay_i])
);
end
endgenerate

//// Address

genvar addr_i;
generate
for(addr_i = 0; addr_i < C_MEM_ADDR_WIDTH; addr_i = addr_i + 1) begin : gen_addr_obuft
OBUFT iob_addr_inst
(.I ( ioi_addr_delay[addr_i]),
.T ( t_addr_delay[addr_i]),
.O ( mcbx_dram_addr[addr_i])
);
end
endgenerate

This adds ODELAY components to each address bit.

Step 3 - Run the MIG design again through Synthesis, Implementation, and BitGen using the MIG provided "ise_flow.bat" file (located in the 'example_design/par' and 'user_design/par' directories).

Test the modified ".bit" file in hardware to see if the data errors still occur. If the data errors are resolved, the Engineering Sample does exhibit this address bit hold violation errata item. This issue is scheduled to be resolved in production silicon and the above noted ODELAY work-around can be used in the interim.