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AR# 34092

System Generator for DSP 11.4 - The automatic constraints written by System Generator do not appear to properly cover all of the paths in my design


When my design contains even and odd rates relative to the system rate, the constraints do not always cover the paths between these domains properly.  Additionally, if I use the CE probe block output as a data signal, System Generator does not identify this as a system rate path.


This behavior is due to a known issue in System Generator for DSP.  When there are even and odd rates, the worst case path between these domains is the full system clock rate; however, sometimes System Generator creates a From/To constraint that is a multi-cycle constraint instead. 

To work around this issue, you can manually modify the cross clock domain From/To constraints.

If you are experiencing problems with the constraints for either of these reasons, please open a WebCase with Xilinx Technical Support.

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AR# 34092
Date Created 02/23/2010
Last Updated 05/23/2014
Status Archive
Type General Article