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AR# 34101

Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - cfg_err_cpl_unexpect_n port is not available


The Reporting User Error Conditions of the Spartan-6 FPGA Integrated Block for PCI Express User Guide (UG654) lists cfg_err_cpl_unexpected_n in Table 6-14. This signal is not a valid port on the block and does not exist in the wrapper design. The Migration Considerations chapter correctly identifies this signal as not existing on the Spartan-6 FPGA integrated block.


Remove the cfg_err_cpl_unexpect_n port from the design. Receiving an unexpected completion is considered an Advisory Non-Fatal Error condition. Since Spartan-6 devices do not support Advanced Error Reporting (AER), if the user application receives an unexpected completion, it should be discarded and no error is reported. This indicates a routing problem within the system. Eventually, the component that initiated the original request that resulted in the incorrectly routed completion will experience a completion timeout and the problem is then identified.
For more information on this type of error, see section of the PCI Express specification v1.1.

Revision History
1/12/2010 - Initial Release
AR# 34101
Date 05/23/2014
Status Archive
Type Known Issues
  • Spartan-6 LXT
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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