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AR# 34105

CPRI v2.2/v2.3 - MMCM settings is incorrect for the hires clock generation


The CPRI core's clocking example design uses incorrect MMCM multiply and divide values to generate the hires clock.

The MMCM in the example designmay not lock,failing to generate the appropriate hires clock.

MMCMs used in the coreare notaffected by this issue.


The following settings should be changed on the MMCM instantiation to change the VCO to 1000 MHz, which is well above the 600 MHz minimum. Also, change to use a 100 MHz input rather than 122.88 to provide a clear differentiation between the hires clk and the ref clk.

6G mode:
CLKFBOUT_MULT_F from 5.5 to 10
CLKOUT0_DIVIDE_F from 2.0 to 3.0
clkin from 122.88 to 100MHz

3G mode:
CLKFBOUT_MULT_F from 4 to 10
CLKOUT0_DIVIDE_F from 2.0 to 5.0
clkin from 122.88 to 100MHz

This issue will be fixed in the V3.1 core released with ISE tools 12.1.

Please contact Xilinx Technical Support if you need further assistance.

AR# 34105
Date Created 02/04/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • CPRI