We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34106

OBSAI v3.1 - MMCM settings are incorrect for hires clock generation


The OBSAI core's clocking example design uses incorrect MMCM multiply and divide values to generate the hires clock.

The MMCM in the example design may not lock, failing to generate appropriate the hires clock.

MMCMs used in the core are not affected by this issue.


The following settings should be changed on the MMCM instantiation to change the VCO to 700 MHz, which is well above the 600 MHz minimum.

CLKFBOUT_MULT_F from 10.5 to 14.0
CLKOUT0_DIVIDE_F from 3.0 4.0
CLKOUT1_DIVIDE from 21 to 28

This issue will be fixed in the V4.1 core released with ISE tools 12.1.

Please contact Xilinx Technical Support if you need further assistance.

AR# 34106
Date Created 01/11/2010
Last Updated 02/04/2010
Status Active
Type General Article
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4