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AR# 34110

Virtex-5 FPGA GTX RocketIO - Simulation warnings when using the fabric clock correction module

Description

When simulating the example design generated by the GTX RocketIO Wizard generated for an odd number of clock correction bytes, it is possible to see the following warning:

"Warning : At time 55134250, RDEN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl k1 is high when RST is high. RDEN should be low during reset.
Warning : At time 55134250, WREN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl k1 is high when RST is high. WREN should be low during reset."

Solution

This warning is the result of some signals not being defined at the beginning of the simulation and can be safely ignored. The default statements in the controlling state machines ensure that the signals are correctly set in hardware and, as such, it is not a problem in an actual system.
AR# 34110
Date Created 01/12/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-5 TXT
  • Virtex-5 FXT
IP
  • Virtex-5 RocketIO GTX Transceiver Wizard