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AR# 34115 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

Description

Synthesizing the Endpoint Block Pus Wrapper for PCI Express gives the following warning message:

WARNING:Xst:2016 - Found a loop when searching source clock on port 'u_pcie_phy_top/u_pcie_gt_v6fxt_1lane/pcie_gt_i/gtx_v6_i/GTXD[0].GTX:TXOUTCLK'

Can this warning message be ignored?

Solution

The above warning message is incorrectly reported by the XST. It will be corrected in a future release. This warning message can be safely ignored.

Revision History
04/23/2010 - Updated for ISE 12.1 and core version v1.5
03/23/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Actions

AR# 34115
Date Created 03/23/2010
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 11.4
IP
  • Endpoint Block Wrapper for PCI Express
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