^
Advanced Search

AR# 34120 11.3 Virtex-6/-5 Pack - Inversion not pushed into Output FF input

Description

My design has an Inverter driving the input of a flip-flop (FF) that is being packed into an OLOGIC component. There is an inversion mux available on the input path to the FF for the D1,D2,T1,T2 pins. Why is the inverter being implemented as a Slice LUT instead of being pushed into the OLOGIC inversion mux? The timing of the path would be much better without the LUT delay.

Solution

The problem with pushing the Inverter to the FF is that MAP has to make this descision before it is known for sure that the FF will be packed into an OLOGIC component. Even if the FF has an IOB=TRUE property, the OLOGIC pack might fail for connectivity reasons and the FF is packed into a Slice where there is no way to implement the inversion (since there is no inversion mux in that path).

Now that Pack supports the new IOB=FORCE property (pack FF in OLOGIC or error), it is possible to ensure that the FF will not be packed into a Slice. Beginning with ISE version 12.1, MAP pushes the inversion to the FF if an IOB=FORCE property is on the FF.


OLOGIC Component with Inversion Mux in Input Path to FF


Slice Component with No Inversion Mux in Input Path to FF

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37213 Virtex-6 FPGA Design Assistant - Troubleshoot common fabric problems N/A N/A

Actions

AR# 34120
Date Created 01/14/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • Less
Feed Back