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AR# 34146 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after Installing 11.4.1

Description

After installing ISE 11.4.1 design tools update, designs using the Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express may fail a "Pin to Pin Skew Constraint" even though the Timing Score is 0. For more information about 11.4.1, see (Xilinx Answer 34019).

Solution

It would show up in the PAR report similar to this:

Article 34146 Figure 1
Article 34146 Figure 1


And the timing report would show:

Article 34146 Figure 2
Article 34146 Figure 2

This error can be safely ignored. It is not a legitimate failure due to incorrect skew analysis by the software. This problem is being fixed and planned to be fixed in ISE 12.1.

Revision History
01/26/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

Actions

AR# 34146
Date Created 01/18/2010
Last Updated 01/21/2013
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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