AR# 34149: LogiCORE FIR Compiler - When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device?
AR# 34149
LogiCORE FIR Compiler - When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device?
Description
When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device?
Solution
This issue has been fixed in the FIR Compiler v5.0
Please see (Xilinx Answer 29138) for a detailed list of LogiCORE IP FIR Compiler Release Notes and Known Issues.