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AR# 34153 Spartan-6 FPGA MCB - Can MCB pins be swapped to help facilitate board layout?

Description

When interfacing between the MCB and an external SDRAM memory component, you must use the predefined MCP pin I/O locations. The MIG tool generates a UCF to LOC the required pins properly. However, to facilitate board layout, it might be desirable to swap MCB pins. This Answer Record details the pins that can and cannot be swapped.

Solution

Allowed Pin Swaps
  • DQ bit swapping at the memory interface. Swapping can only be done within a data-byte group.
  • Upper and lower byte lanes at an x16 memory interface. Swapping can only be done when the whole data-byte group, corresponding DQS pairs, and DM are swapped with each other.

Prevented Pin Swaps
  • Control pins (that is, RAS, CAS, WE, CKE, RESET, and ODT)
  • Address pins (BA and A) - The address pins are used to program mode registers during initialization. Also, bit A10 is used to control auto-precharge. These pins cannot be swapped.
  • UDM and LDM cannot be swapped as they correspond to the upper and lower data groups within the MCB and at the memory interface.
  • DQS differential pairs (DQS with DQS_n, UDQS with UDQS_n, LDQS with LDQS_n). DQS has specific requirements during the read and write operation as defined by JEDEC. Swapping these pairs would violate these requirements.
  • Upper and lower DQS pairs (UDQS/UDQS_n with LDQS/LDQS_N) as they correspond to the upper and lower data groups within the MCB and at the memory interface.
Additional Pin Rules
  • For pin information on RZQ and ZIO, please see (Xilinx Answer 34055).
  • The active-Low Chip Select (CS#) pin of the target memory device should be connected to ground on the board. Because the MCB only supports connections to a single memory component, it does not provide a signal to control the CS# input. If necessary, contact your memory vendor for more information.

Actions

AR# 34153
Date Created 01/27/2010
Last Updated 07/27/2011
Status Active
Type
IP
  • MIG
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