Main
Home  :  Support  :  Answers  :  SPI-4.2 v9.3 - Virtex-6 core should not be used in production due to potential block RAM memory collision

SPI-4.2 v9.3 - Virtex-6 core should not be used in production due to potential block RAM memory collision

AR# 34155

Search For Another Answer
Topic Telecommunications
Last Updated 05/03/2010
Status Active
Description

The SPI-4.2 v9.3 core has the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking, documented in the Virtex-6 FPGA Memory Resources User's Guide (UG363). This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.

Solution

This issue is fixed in v9.3 Rev1 of the core. For more information, see (Xilinx Answer 33313).
Applies To

Devices

  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT

IP

  • SPI-4 Phase 2 Interface Solutions
 
 
/csi/footer.htm