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AR# 34156 SPI-4.2 Lite v5.1 - Virtex-6 core should not be used in production due to potential block RAM memory collision

Description

The SPI-4.2 Lite v5.1 core has the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking, documented in the Virtex-6 FPGA Memory Resources User's Guide(UG363). This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.

Solution

This issue is fixed in the SPI-4.2 Lite v5.1 Rev2 Core available in the ISE 11.5 software.

Actions

AR# 34156
Date Created 01/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
IP
  • SPI-4 Phase 2 Interface Solutions
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