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AR# 34157

SPI-3 Link Layer v7.1 - Virtex-6 FPGA core should not be used in production due to potential block RAM memory collision


The SPI-3 Link Layer v7.1 core has the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking, documented in the Virtex-6 FPGA Memory Resources User's Guide (UG363). This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.


This issue is fixed in v7.1 Rev1 of the core available in ISE 11.5
AR# 34157
Date Created 01/20/2010
Last Updated 05/23/2014
Status Archive
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.4
  • SPI-3 Link Layer Interface, Multi-channel