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AR# 34159 LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors

Description

In Virtex-6 FPGA instances of the XAUI v9.1 core using the 32-bit XGMII interface, the MMCM parameter values used in the example design will result in a MMCM VCO frequency that is now below the newly specified minimum. This will result in DRC failures in the next release of the ISE Design Suite software.

For more details on the MMCM issue, see (Xilinx Answer 33849).

Solution

Depending on how the core was configured at generation time, there could be zero, one, or two instances of the MMCM in the example design. Each of the MMCM parameter values should be changed as follows:

CLKFBOUT_MULT_F: from 3.0 to 6.0
CLKOUT0_DIVIDE_F: from 3.0 to 6.0
CLKOUT1_DIVIDE: from 3 to 6

Actions

AR# 34159
Date Created 01/22/2010
Last Updated 01/22/2010
Status Active
Type
Devices
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 CXT
Tools
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.3
IP
  • XAUI
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