In Virtex-6 FPGA instances of the 10-Gigabit Ethernet MAC v9.3 core, the MMCM parameter values used in the example design will result in a MMCM VCO frequency that is below the newly specified minimum.
This will result in DRC failures in the next release of the ISE Design Suite software.
For more information on the MMCM, see (Xilinx Answer 33849).
Depending on how the core was configured at generation time, the MMCM instances could appear in one or two locations in the example design.
Each of the MMCM parameter values should be changed as follows:
CLKFBOUT_MULT_F: from 3.0 to 6.0
CLKOUT0_DIVIDE_F: from 3.0 to 6.0
CLKOUT1_DIVIDE: from 3 to 6