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AR# 34162

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Block RAM parameterization might result in memory collisions during simulation and erroneous operation


In the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC wrapper version 1.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):

Specifically, RAMB36E1 instances within the LocalLink FIFO level of hierarchy are configured for READ_FIRST TDP mode, but do not respect the requirement that read and write addresses cannot be within the same page of memory. When using ISE tools 11.4, this might result in memory collisions reported during simulation. Additionally, using ISE tools 11.3 or 11.4 might result in marginal or erroneous hardware operation of the block RAM.


Files named rx_client_fifo_[8 | 16].v[hd] and tx_client_fifo_[8 | 16].v[hd] exist in the example_design/client/fifo subdirectory. In each file is a single instance of the primitive RAMB36E1 which contains attributes called WRITE_MODE_A and WRITE_MODE_B. Change both the WRITE_MODE_A and WRITE_MODE_B values from "READ_FIRST" to "WRITE_FIRST".  

This issue is scheduled to be fixed in the ISE tools 11.5 release of the core.

Linked Answer Records

Master Answer Records

AR# 34162
Date Created 01/18/2010
Last Updated 05/23/2014
Status Archive
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.3
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper