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AR# 34163 LogiCore IP XAUI v9.1 - The Spartan-6 FPGA Example Design does not implement the DCM_SP attribute setting for "CLK_FEEDBACK"

Description

TheSpartan-6 FPGA Example Design does not implement the DCM_SP attribute setting for "CLK_FEEDBACK".

Solution

The CLK_FEEDBACK attribute for the DCM_SP primitive should be set as folllows:

Verilog Example Design

.CLK_FEEDBACK("2X")

VHDL Example Design

CLK_FEEDBACK => "2X"

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33302 LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33302 LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 N/A N/A

Actions

AR# 34163
Date Created 01/22/2010
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
IP
  • XAUI
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