Due to changes in the routing models of the Virtex-6 FPGA, all Virtex-6 designs must be re-run through implementation in a version of ISE Design Suite software later than 11.4. These changes have been implemented in ISE versions 11.5 and later.
To create a valid design, existing designs must be re-run through implementation (at minimum MAP and PAR) in 11.5 or later ISE Design Suite software.