The Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express can be generated with a VHDL example design. This is the PIO design found in the example_directoryof the generated core. However, there is no VHDL testbench generated.
This article provides the VHDL testbench files.
To obtain the VHDL testbench files, download the following ZIP file:
Unzip this file on top of your generated core's component name directory. For example, if you named the generated component s6_pcie_core, then unzip the ZIP file onto the s6_pcie_core directory. The VHDL testbench files are placed in the simulation directory along with new simulation scripts to enable VHDL simulation with ModelSim and NC-SIM.
1/27/2010 - Corrected ZIP file link
1/19/2010 - Initial Release