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AR# 34174

13.2 Timing Analysis/PlanAhead - Why is there a discrepancy between the Timing Analyzer package trace delay estimates and analytical parasitic delay (SQRT(LC))?

Description

The flight time through the package is fundamental for the timing analysis of device-to-device interfaces and deskew operations.

Before ISE software release 13.2, the flight time in the PlanAhead and Timing Analyzer tools were calculated with an approximated formula, multiplying the package length by 6.0 ps/mm (min) or 7.1 ps/mm (max).

The methodology of using a single coefficient to convert length to delay can be erroneous, especially for short trace lengths.

Starting from ISE13.2 tools for 7 series, the flight time will be calculated using the precise SQRT(LC) formula.

Solution

The theory is that the parasitic capacitance of the die bump where the traces bond to Si is not fully accounted for when using the 6.5 ps/mm coefficient. This additional capacitance may be really significant for short traces, while it may not be for medium traces, and is not compensated for in the 6.5 and reflects in the long and short delays. The recommendation (Pg 125 of ver 1.7) in theVirtex-6 FPGA Memory Interface Solutions (UG 406) needs to be used with some caution.

Recommendation to analytically estimate package trace delay

"L" and "C" of the package are information provided with the IBIS models package file. This comes from Sigrity XtractIM simulation and can be considered precise up to (conservatively) 5%.

The delay due to the package is a function of the trace inductance and capacitance. In the IBIS model, the package impedance per package length is provided in the package file, thus the flight time calculation is easy.

If L and C in the IBIS model are respectively the inductance and capacitance per package length, the propagation time in the package is given by SQRT(LC).

For example:

For a Virtex-5 FPGA IBIS model, the package ff323_5vlx20t_ibis.pkg is provided. Let us choose the pin B9.
From Capacitance matrix, C=1.58E-12 F/package length
From Inductance matrix, L=1.99E-09 H/package length
Delay= SQRT(C*L)=56.1 ps

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34558 MIG Virtex-6 DDR2/DDR3 - Trace Matching Guidelines N/A N/A
AR# 34174
Date Created 01/19/2010
Last Updated 11/06/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
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Tools
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  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • PlanAhead - 11.1
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