Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Patch to Enable VHDL File Generation

Description

The Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express does not generate VHDL files. This article provides a patch that enables VHDL file generation.

Solution

To obtain the VHDL testbench files, download the following ZIP file: 

http://www.xilinx.com/txpatches/pub/swhelp/ise11_updates/ar34182_v6_pcie_v1_4_1.zip

Install the patch by extracting the contents of the ".zip" archive to the root directory of XILINX (the Xilinx ISE installation) as pointed to by your XILINX environment variable. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive. 

NOTE: Xilinx recommends backing up the following directory before unzipping the file:
%XILINX%\11.1\ISE\coregen\ip\xilinx\network\com\xilinx\ip\v6_pcie_v1_4

Revision History

01/22/2010 - Initial Release