When I attempt to place a clock pin on a valid site (for example: GCLK0 Pin) using pre-synthesis pin planning, I get a warning and error similar to the following:
This error seems to occur for Automotive Spartan-3A/E devices only.
I am able to perform this task on other Spartan-3A and Spartan-3E devices.
Why does this happen?
Applying UCF constraints post synthesis works without issue.
This is a known issue in the PlanAhead software where it does not allow the placement of clock pins on GCLK pins for Automotive Spartan-3A/E devices.
To work around the issue, use post synthesis I/O planning or apply them directly through the UCF constraints file.