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AR# 34200

Design Assistant for PCI Express - How to keep signals from getting optimized out so they can be found with ChipScope Inserter


Unless a signal is an output of a register or other device primitives, it might not show up in the ChipScope inserter due to optimization performed by XST. Is there a way to ensure a signal is visible in XST? This also applies to unused ports on the core that might not be hooked up in the design, but are needed for debug purposes.

Note: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.



To preserve a net, Verilog uses the "keep" constraint.

Example for an output port:

(*keep= "true"*)
output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_lstatus,

Example for a wire:

(*keep= "true"*)
wire trn_tdst_rdy;


Use the KEEP constraint in VHDL as well.

For a core output port that needs to be preserved add the following before the end keyword:

sys_clk : in std_logic;
sys_reset_n : in std_logic
attribute keep : string; -- this only needs to be added once
attribute keep of cfg_lstatus : signal is "true";
end v6_pcie_v1_4;

For any signal:

attribute keep : string; -- this only needs to be added once
attribute keep of trn_tdst_rdy_n: signal is "true";

Revision History
7/30/2011 - Initial Release

AR# 34200
Date Created 07/29/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )